1. Field of the Invention
This invention relates to a semiconductor storage device, and more particularly to a semiconductor storage device having memory cells formed from non-volatile transistors.
2. Description of the Related Art
In order to achieve high efficiency in productivity of semiconductor storage devices (semiconductor memories), it is crucial to enhance the yield in production of chips. However, as semiconductor memories continue to increase in capacity as a result of the advance of a fine working techniques in recent years, pattern defects caused by dust or similar foreign matter have also progressively increased, with the result that many chips are selectively determined to be unacceptable because several defective memory cells are produced in a memory cell block, or a row line or a column line is disconnected or short-circuited by a pattern defect. Therefore, potential for increased productivity by enhancement of the yield in production of chips is approaching its limit. Here, a redundancy relief method is commonly employed as a means of changing unacceptable chips to acceptable articles. According to this method, spare memory cells and a redundancy control circuit are provided in a chip so that defective memory cells may be replaced with the spare memory cells.
The redundancy relief method is a method wherein, for example, spare memory cells for column lines, spare memory cells for row lines, fuse circuits for column line redundancy switching information, fuse circuits for row line redundancy switching information and a redundancy switching control circuit are provided, and redundancy switching information is stored in advance in the fuse circuits. Defective memory cells are replaced with the column line spare memory cells or the row line spare memory cells in accordance with the redundancy switching information.
In a volatile memory integrated circuit such as a DRAM or an SRAM, polycrystalline silicon is normally used for fuse elements constituting a fuse circuit. In this instance, an inspection step of chips is time consuming because a step of fusing polycrystalline silicon using a laser or some other suitable means to store redundancy switching information is required before the fuse element is enclosed into a package. In contrast, in an EPROM or a flash memory which is a non-volatile memory integrated circuit, memory cells are constituted from electrically writable non-volatile transistors. In addition, a fuse circuit can be constructed using a fuse element constituted from a non-volatile transistor. Because redundancy switching information can be electrically written into a fuse circuit, a fuse circuit can be easily used in taking the counter-measure of redundancy switching relief against unacceptable chips. However, since fuse circuits, a fuse circuit write voltage supply circuit and a fuse circuit write control circuit are required, the area occupied by those peripheral circuits tends to be large.
Further, with the increase in capacity of CPUs in recent years, there has been an increasing demand for semiconductor memory integrated circuits of a multi-bit output configuration, and a large-scale redundancy switching construction must be adopted in accordance with a multi-bit output configuration. This has resulted in an increase in the area occupied by peripheral circuits, and consequently, a further increase in the size of the chips.
FIG. 1 is a block diagram showing an example of a conventional semiconductor storage device having memory cells formed from non-volatile transistors.
Semiconductor storage device 100 includes two memory cells 120.sub.1 and 120.sub.2, two column line spare memory cell blocks 121.sub.1 and 121.sub.2, six row pre-decoders 110.sub.1 to 110.sub.6, address buffer 111, twelve row decoders 112.sub.11 to 112.sub.62 from each of which four column lines are outputted, two column selectors 113.sub.1 and 113.sub.2 from each of which four column lines are outputted, two redundancy switching circuits 114.sub.1 and 114.sub.2 from each of which a single spare column line is outputted, two sense amplifiers 115.sub.1 and 115.sub.2, a redundancy switching control circuit 116, a fuse circuit write control circuit 117, six fuse circuits 118.sub.1 to 118.sub.6, and a fuse circuit write voltage supply circuit 119. Here, redundancy switching circuits 114.sub.1 and 114.sub.2, redundancy switching control circuit 116, fuse circuit write control circuit 117 and fuse circuits 118.sub.1 to 118.sub.6 function as a redundancy circuit for replacing column line memory cells including defective memory cells produced in memory cell blocks 120.sub.1 and 120.sub.2 with column line spare memory cells in column line spare memory cell blocks 121.sub.1 and 121.sub.2.
Memory cell block 120.sub.1 on the left side of FIG. 1 is constituted from 4.times.4.times.6=96 memory cells constituted from non-volatile transistors arranged at cross points between four row lines outputted from each of row decoders 112.sub.11 to 112.sub.61 and four column lines outputted from column selector 113.sub.1. It is to be noted that "column line memory cells" denotes four memory cells arranged at cross points between four row lines outputted, for example, from row decoder 112.sub.11 and one column line outputted from column selector 113.sub.1. Memory cell block 120.sub.2 on the right side of FIG. 1 is constructed in a similar manner to memory cell block 120.sub.1.
Column line spare memory cell block 121.sub.1 on the left side of FIG. 1 is constituted from 4.times.1.times.6=24 spare memory cells constituted from non-volatile transistors arranged at cross points between four row lines outputted from each of column decoders 112.sub.11 to 112.sub.61 and one spare column line outputted from redundancy switching circuit 114.sub.1, and is constituted from six column line spare memory cells for switching by column line memories including defective memory cells produced in memory cell block 120.sub.1. It is to be noted that "column line spare memory cells" denotes four spare memory cells arranged, for example, at cross points between four row lines outputted from row decoder 112.sub.11 and one spare column line outputted from redundancy switching circuit 114.sub.1. Column line spare memory block 121.sub.2 on the right side of FIG. 1 is constructed in a similar manner to column line spare memory cell block 121.sub.1.
Six row pre-decoders 110.sub.1 to 110.sub.6 are connected to address buffer 111 by way of first address signal lines L.sub.AD1 and select rows of memory cell blocks 120.sub.1 and 120.sub.2. Twelve row decoders 112.sub.11 to 112.sub.62 are connected two-to-one to row pre-decoders 110.sub.1 to 110.sub.6 by way of first to sixth pre-row lines L.sub.PC1 to L.sub.PC6, respectively. Specifically, row decoder 112.sub.11 and row decoder 112.sub.12 are connected to row pre-decoder 110.sub.1 by way of first pre-row line L.sub.PC1 ; row decoder 112.sub.21 and row decoder 112.sub.22 are connected to row pre-decoder 110.sub.2 by way of second pre-row line L.sub.PC2 ; row decoder 112.sub.31 and row decoder 112.sub.32 are connected to row pre-decoder 110.sub.3 by way of third pre-row line L.sub.PC3 ; row decoder 112.sub.41 and row decoder 112.sub.42 are connected to row pre-decoder 110.sub.4 by way of fourth pre-row line L.sub.PC4 ; row decoder 112.sub.51 and row decoder 112.sub.52 are connected to row pre-decoder 110.sub.5 by way of fifth pre-row line L.sub.PC5 ; and row decoder 112.sub.61 and row decoder 112.sub.62 are connected to row pre-decoder 110.sub.6 by way of sixth pre-row line L.sub.PC6.
Two column selectors 113.sub.1 and 113.sub.2 are provided to select columns of memory cell blocks 120.sub.1 and 120.sub.2, respectively. Here, column selector 113.sub.1 on the left side of FIG. 1 is connected to address buffer 111 by way of first column address signal line L.sub.RAD1 and connected to redundancy switching circuit 114.sub.1 on the left side of FIG. 1 by way of first data line L.sub.D1. Meanwhile, column selector 113.sub.2 on the right side of FIG. 1 is connected to address buffer 111 by way of first column address signal line L.sub.RAD1 and connected to redundancy switching circuit 114.sub.2 on the right side of FIG. 1 by way of second data line L.sub.D2.
The two redundancy switching circuits 114.sub.1 and 114.sub.2 are provided to replace data from memory cell blocks 120.sub.1 and 120.sub.2 with data from spare memory cell blocks 121.sub.1 and 121.sub.2, respectively. Here, redundancy switching circuit 114.sub.1 on the left side of FIG. 1 is connected to sense amplifier 115.sub.1 on the left side of FIG. 1 by way of third data line L.sub.D3 and connected to redundancy switching control circuit 116 by way of first control signal line L.sub.C1. Meanwhile, redundancy switching circuit 114.sub.2 on the right side of FIG. 1 is connected to sense amplifier 115P.sub.2 on the right side of FIG. 1 by way of fourth data line L.sub.D4 and connected to redundancy switching control circuit 116 by way of second control signal line L.sub.C2.
Redundancy switching control circuit 116 refers to redundancy switching information written in fuse circuits 118.sub.1 to 118.sub.6 and provides to redundancy switching circuits 114.sub.1 and 114.sub.2 an instruction as to whether or not data from memory cell blocks 120.sub.1 and 120.sub.2 should be switched to data from spare memory cell blocks 121.sub.1 and 121.sub.2, respectively. It is to be noted that redundancy switching control circuit 116 is connected to address buffer 111 by way of second column address signal line L.sub.RAD2 and connected to fuse circuits 118.sub.1 to 118.sub.6 by way of eleventh to sixteenth signal lines L.sub.S11 to L.sub.S16, respectively.
Six fuse circuits 118.sub.1 to 118.sub.6 are constituted from fuse elements formed from non-volatile transistors having the same structure as the memory cells described above and are provided so that redundancy switching information may be provided therein. It is to be noted that fuse circuits 118.sub.1 to 118.sub.6 are connected to fuse circuit write voltage supply circuit 119, and are also connected to fuse circuit write control circuit 117 by way of 21st to 26th signal lines L.sub.S21 to L.sub.S26, respectively.
Fuse circuit write control circuit 117 is provided to write redundancy switching information into fuse circuits 118.sub.1 to 118.sub.6 and is connected to address circuit 111 by way of second address signal line L.sub.AD2. Meanwhile, fuse circuit write voltage supply circuit 119 is provided to supply to fuse circuits 118.sub.1 to 118.sub.6 a voltage necessary to write redundancy switching information.
Next will be described redundancy switching control of semiconductor storage device 100.
In a read mode, one of six row pre-decoders 110.sub.1 to 110.sub.6 is selected in response to a row address signal outputted from address buffer 111 on first address signal line L.sub.AD1. If it is assumed that, for example, row pre-decoder 110.sub.1 shown uppermost in FIG. 1 is selected, one of the four row lines outputted from each of row decoders 112.sub.11 and 112.sub.12 is selected by row decoders 112.sub.11 and 112.sub.12 which are connected to thus selected row pre-decoder 110.sub.1 by way of first pre-row line L.sub.PC1.
In column selector 113.sub.1 on the left side of FIG. 1, one of the four column lines of memory cell block 120.sub.1 on the left side of FIG. 1 is selected in response to a first column address signal outputted from address buffer 111 on first column address signal line L.sub.RAD1, and data on the selected column line are outputted to redundancy switching circuit 114.sub.1 on the left side of FIG. 1. In redundancy switching circuit 114.sub.1, data switching between data from column selector 113.sub.1 and data from column line spare memory cell block 121.sub.1 is performed in response to a first control signal outputted from redundancy switching control circuit 116 on first control signal line L.sub.C1, and the data are outputted to sense amplifier 115.sub.1 on the left side of FIG. 1. Sense amplifier 115.sub.1 amplifies the data transmitted thereto from redundancy switching circuit 114.sub.1 and outputs the amplified data to an output buffer circuit (not shown). Column selector 113.sub.2, redundancy switching circuit 114.sub.2 and sense amplifier 115.sub.2 shown on the right side of FIG. 1 operate in a manner similar to that described above.
Redundancy switching control circuit 116 produces first and second control signals instructing which column line memory cells of memory cell blocks 120.sub.1 and 120.sub.2 should be replaced with column line spare memory cells in accordance with the redundancy switching information written in fuse circuits 118.sub.1 to 118.sub.6. The thus-produced first and second control signals are outputted to redundancy switching circuits 114.sub.1 and 114.sub.2 by way of first and second control signal lines L.sub.C1 and L.sub.C2, respectively.
If a defective memory cell is found, for example, in memory cell block 120.sub.1 on the left side of FIG. 1 during an inspection step before shipment, redundancy switching information instructing the replacement of column line memory cells including the thus-found defective memory cell with column line spare memory cells in column line spare memory cell block 121.sub.1 must be written into fuse circuits 118.sub.1 to 118.sub.6. In such a redundancy switching information write mode, a high voltage necessary to write is supplied from fuse circuit write voltage supply circuit 119 to fuse circuits 118.sub.1 to 118.sub.6, and redundancy switching information is selectively written into fuse circuits 118.sub.1 to 118.sub.6 by fuse circuit write control circuit 117 in accordance with an address signal outputted from address buffer 111 to second address signal line L.sub.AD2.
However, in the semiconductor storage device 100 described above (a semiconductor memory integrated circuit such as, for example, an EPROM or a flash memory), while a redundancy switching countermeasure can be easily performed during an inspection step, the necessity for a fuse circuit write voltage supply circuit 119, fuse circuit write control circuit 117 and other circuits tends to increase the area occupied by the peripheral circuits. If large-scale configuration of redundancy circuits is considered in the future, the increase in chip size will result in lower productivity or lower yield in production, with the result that productivity cannot be improved.
The crucial component in realizing a large-scale redundancy circuit is the fuse circuit write control circuit. While the fuse circuit write control circuit is not directly involved when a user uses the memory product, its function is essential for selecting a fuse circuit into which redundancy switching information should be written for replacing defective memory cells with spare memory cells. Another significant obstacle to reducing chip size is the wiring from the address buffer, since a fuse circuit write control signal necessary to select a fuse circuit by means of the fuse circuit write control circuit is obtained by way of address input terminals.
3. Summary of the Invention
It is an object of the present invention to provide a semiconductor storage device by which improvement in productivity can be achieved even if a redundancy circuit is increased in scale.
A semiconductor storage circuit according to the present invention includes:
a memory cell block in which memory cells formed from non-volatile transistors are arranged two-dimensionally, PA1 a spare memory cell block constituted from a plurality of spare memory cells to be replaced defective memory cells produced in the memory cell block, PA1 a plurality of row pre-decoder circuits for selecting a row of the memory cell block, PA1 a plurality of fuse circuits which are constituted from fuse elements formed from non-volatile transistors of the same structure as those of the memory cells and which are adapted to write redundancy switching information therein, PA1 a fuse circuit write voltage supply circuit for supplying to the fuse circuits a voltage necessary to write the redundancy switching information, PA1 a redundancy switching circuit for switching data from the memory cell block to data from the spare memory cell block, and PA1 a redundancy switching control circuit for referring to the redundancy switching information written in the fuse circuits to provide to the redundancy switching circuit an instruction whether or not the data from the memory cell block should be switched to the data from the spare memory cell block; PA1 and is characterized in that:
the plurality of row pre-decoder circuits and the plurality of fuse circuits are connected in a one-by-one corresponding relationship to each other, and PA2 one of the plurality of fuse circuits is selected by the plurality of row pre-decoder circuits and the redundancy switching information is written into each of the fuse circuits.
In the semiconductor storage device of the present invention, the plurality of row pre-decoder circuits and the plurality of fuse circuits are connected to each other in a one-by-one corresponding relationship, and one of the plurality of fuse circuits is selected by the plurality of row pre-decoder circuits, and redundancy switching information is written into each fuse circuit. Consequently, there is no necessity for a fuse circuit write control circuit and associated wiring lines which are conventionally required to write redundancy switching information into the fuse circuits.